[HGI-news-int] [Call for Papers] DATE 2017 - A5 Track "Secure Systems, Circuits, and Architectures"

[English Newsletter of the Horst Goertz Institute of IT Security in Bochum]

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                               CALL FOR PAPERS

            DESIGN AUTOMATION AND TEST IN EUROPE CONFERENCE (DATE)
            TOPIC A5: "SECURE SYSTEMS, CIRCUITS, AND ARCHITECTURES"

                               DRESDEN, GERMANY
                             19TH-23RD MARCH 2018
                        http://www.date-conference.com
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DEADLINES
- Paper Submissions           September 10, 2017
- Notification of Acceptance  November 10, 2017
- Camera-Ready Paper          November 30, 2017
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QUICK LINKS
- Conference http://www.date-conference.com
- Call for Papers http://www.date-conference.com/call-for-papers
- Author Instructions http://www.date-conference.com/submission-instructions
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The DATE 2018 conference and exhibition is the main European event
bringing together designers and design automation users, researchers and
vendors, as well as specialists in the hardware and software design,
test and manufacturing of electronic circuits and systems.

You are invited to submit your research contributions to the Topic A5

	  "SECURE SYSTEMS, CIRCUITS, AND ARCHITECTURES"

that welcomes all submissions covered by the following abstract:

Secured systems need a combination of hardware, software and embedded
techniques to succeed. Indeed, the weakest link in the security chain
determines the overall system security. This topic therefore invites
papers on novel technology and experiences for specific security
problems as well as overall design integration and validation methods
for secure circuits, systems-on-chip and embedded systems.
Topics of interest cover specific aspects of secure circuits and
architectures with an emphasis on design experiences, real system
deployments, applications, and prototypes. This also includes secure
HW architectures; novel architectures for embedded cryptography;
demonstrations with fault or other physical attacks; embedded
processors or co-processors for security; off-chip memories and
network-on-chip enciphering and integrity checking; demonstrations
of HW-enabled security on real systems or prototypes; logic-level
security; firmware security.

Submissions are limited to 6 pages for oral-presentation papers,
and 4 pages for interactive-presentation papers (2 columns, blind
submission policy).

Authors of accepted papers with outstanding results of particular
interest for the community will receive an invitation to submit an
extended version of their work to a special section of
*IEEE Transactions on Computers*.

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TOPIC TECHNICAL COMMITTEE

Todd Austin, University of Michigan, US
Aydin Aysu, University of Texas at Austin, US
Luca Breveglieri, Politecnico di Milano, IT
Aurélien Francillon, EURECOM, FR
Jorge Guajardo, Bosch Research and Technology Center, Robert Bosch LLC, US
Frank K. Gürkaynak, ETH Zürich, CH
Marcel Medwed, NXP Semiconductors, AT
Thomas Pöppelmann, Infineon Technologies AG, DE
Sergei Skorobogatov, University of Cambridge, GB
Lionel Torres, University of Montpellier, FR
Ingrid Verbauwhede, KU Leuven and UCLA, BE

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FURTHER INFORMATION & TOPIC CHAIRS

Tim Güneysu, Ruhr-Universität Bochum & DFKI, DE - Topic Chair
email: tim.gueneysu at rub.de

Stefan Mangard, TU Graz, DE - Topic Co-Chair
email: Stefan.Mangard at iaik.tugraz.at
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